News

Nextchip license NeuPro-M NPU to bring powerful and highly efficient AI capabilities to boost performance and capabilities of ...
As a member of GF’s GlobalSolutions™ Ecosystem, Thalia brings its cutting-edge AMALIA Platform to a broader audience of GF customers, empowering them to tackle the challenges of design migration ...
The Cadence® DDR5 MRDIMM IP boasts a new high-performance, scalable and adaptable architecture based on Cadence’s proven and highly successful DDR5 and GDDR6 product lines. With multiple engagements ...
As a long-standing member of TSMC OIP Design Center Alliance (DCA), MosChip will spotlight its engineering expertise across advanced technology nodes, packaging, test, and production workflows, with a ...
Equal1, a global leader in silicon powered quantum computing, has announced a major milestone in quantum computing: the successful validation of a commercial CMOS process.
Engineering teams must coordinate across hardware and software domains as system-on-chip (SoC) designs scale in complexity.
The recent HBM4 specification announced by JEDEC is great news for developers of AI training hardware. HBM4 is the latest specification in the rapidly ...
Chip designers are often stuck between a rock and a hard place. Not only are they dealing with staggering design complexity, but they're also under pressure ...
The global semiconductor manufacturing sector, the invisible engine powering the digital age, is undergoing a profound transformation marked by surging demand for artificial intelligence, intensifying ...
The transaction will augment Cadence’s expanding design IP offerings, anchored by a leading portfolio of protocol and interface IP, memory interface IP, SerDes IP at the most advanced nodes, and ...
RIVAI Launched China’s First Fully Self-Developed High- Performance RISC-V Server Chip ...
Designed as an evolutionary step beyond the previous HBM3 standard, JESD270-4 HBM4 will further enhance data processing rates while maintaining essential features such as higher bandwidth, power ...