input wire [9:0] A2address, // (9:0) or 2^10 or 1024, need 31 x 21 = 651 input wire clk_pix, output reg [7:0] A2dout // (7:0) 8 bit pixel value from Alien2.mem (*ROM_STYLE="block"*) reg [7:0] A2memory ...

This port bypasses the DeMiSTify build framework and its git submodules entirely -- no Xilinx/Vivado target exists anywhere in that framework -- and wraps rtl/target_top.vhd directly, in this repo's ...