TSMC's technology roadmap; Intel cuts; reciprocal hacking; McKinsey on IC challenges, ML algorithm table; subsystem chiplets; ...

Complexity, uncertainty, and lots of moving pieces will challenge the semiconductor industry for years to come.

EDA vendors are taking aim at new ways to improve the productivity of design and verification engineers, who are struggling ...

A NoC provides a structured and scalable approach to transporting data between the growing number of IP blocks in a chip.

EDA software is revolutionizing high-speed digital design by accelerating time-to-market despite growing complexity.

It is easy to blame it all on the leading-edge designs. They get all the attention. But there just aren’t enough of them to ...

While analog and digital verification efforts have been essentially separated, closer integration is resulting in a ...

Capturing a granular view of link operation using specialized data packets designed to carry debug information.

Predictive modeling, strategic sampling and embedded monitors help accelerate testing for yield limiting defects.

Early verification of symmetry and IP placement with pattern matching technology has a profound impact on IC design ...

An Assessment Model of Real-World Hardware Security Attacks” was published by researchers at TU Wien and TÜV Austria. “We ...

SCALINX, a fabless semiconductor company specializing in the design of system-on-chip (SoC) devices, was looking to develop a ...