FMIBlog

Manual Wafer Aligner Market Growth 2026–2036 Driven by Cost-Efficient Semiconductor R&D Expansion

As semiconductor manufacturing prioritizes flexibility, innovation, and cost control, manual wafer aligners are expected to ...
Semiconductor Engineering

Innovative Dual Mark Design For Alignment Verification And Process Monitoring In Advanced Lithography

Improving on product overlay is one of the key challenges when shrinking technology nodes in semiconductor manufacturing. . . . With smart placement of alignment mark pairs in the X and Y direction, ...
Nasdaq

Teradyne Announces Production System for Double-Sided Wafer Probe Test for Silicon Photonics

NORTH READING, Mass.--(BUSINESS WIRE)-- Teradyne, a leading provider of automated test equipment, has partnered with ficonTEC, a global leader in production solutions for photonics assembly and test, ...
EDN

EV Group Clears Key Barriers To 3D-IC/TSV High-Volume Manufacturing With Breakthrough Fusion Wafer Bonding Solution

Wafer-to-wafer bonding is an essential process step to enable 3D devices such as stacked DRAM, memory-on-logic and future CMOS image sensors. At the same time, minimizing the dimensions of TSVs, which ...
Semiconductor Engineering

Managing Wafer Retest

Every wafer test touch-down requires a balance between a good electrical contact and preventing damage to the wafer and probe card. Done wrong, it can ruin a wafer and the customized probe card and ...