Semiconductor Engineering

Information Flow Verification Framework Integrating Static and Formal Verification Methods At The Pre-Silicon Stage (U. of Florida)

“Modern system-on-chips (SoCs) are becoming prone to numerous security vulnerabilities due to their ever-growing complexity and size. Therefore, a comprehensive security verification framework is ...
Semiconductor Engineering

Pre-Silicon Verification and Validation Methodology Targeting Robust RISC-V Chip Designs (BSC)

A new technical paper, “Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL,” was published by researchers at Barcelona Supercomputing Center. “The Barcelona ...
Nasdaq

Advantest Introduces SiConic: Groundbreaking Solution for Automated Silicon Validation

TOKYO, Feb. 20, 2025 (GLOBE NEWSWIRE) -- Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857) today unveiled SiConic: a scalable solution for automated silicon validation.
EDN

AI-driven flows ease Arm Neoverse V2 design

Cadence has fine-tuned its AI-driven RTL-to-GDS digital flow, as well as its AI-driven verification flow, for the Arm Neoverse V2 CPU. The company also created corresponding 5-nm and 3-nm Rapid ...