Editor's Note: In Part 3 of this series, consultant and ASIC designer Tom Moxon covered several RTL and logic synthesis design flows. In this installment of the series, he'll describe new physical ...

In IC physical design, there is a tendency to focus on the synthesis and layout tasks, and to not give much consideration to the chip finishing tasks, at least not until the more pressing matters of ...

Techniques for IP reuse have become commonplace in the RTL design world. By contrast, physical design for reuse remains stuck at delivering restrictive “hard IP.†What is holding reuse-design back ...

The FICS Research Institute (University of Florida) has published a new research paper titled “Secure Physical Design.” This is the first and most comprehensive research work done in this area that ...

Security in educational settings is a complex challenge that requires a multi-layered approach. While technology and personnel are crucial components, the physical design of a facility itself plays a ...

Arteris Inc., the inventor and only supplier of silicon-proven commercial network-on-chip (NoC) interconnect IP solutions, today announced availability of Arteris FlexNoC Physical interconnect IP, a ...

Enabling designers to perform block and cell physical verification from within layout environments such as Cadence's Virtuoso is Mentor Graphics' Calibre Interactive. This latest version in a ...

Planning for the physical layout and design of the data center building space should include more than just the equipment room. For example, areas for loading equipment, storage and support personnel ...

But maybe part of the problem isn’t the meetings themselves, but the physical environment and the social norms we’ve constructed around them. For instance, most conference rooms today are anchored by ...

GeekWire chronicles the Pacific Northwest startup scene. Sign up for our weekly startup newsletter, and check out the GeekWire funding tracker and VC directory. by Madeline Vuong on Mar 10, 2016 at 11 ...